Nano-scale characterization of poly-Si gate on high-k gate stack structures by scanning photoemission microscopy

Introduction Scaling and integration of complementary metaloxide-semiconductor devices have made great development in the pursuit of higher performance and lower power consumption. Elemental devices of field effect transistors have been going through a transition from planar to three-dimensional structures for overcoming the physical limitation of thickness for the gate insulator. However, due to the rapid downsizing of devices in the in-plane direction, device analysis for failure caused by concentration of leakage current, and the control of dopant diffusion in thermally treated semiconductors have become more and more difficult. In order to establish guidelines for device fabrication processes, nano-scale characterization of three dimensional device structures becomes an important issue. Photoemission spectroscopy is one of the most powerful techniques to analyze electronic structures such as chemical states of thin films, energy-band discontinuity among heterointerfaces, space charge layers at semiconductor surfaces, and so on. However, the spot size of the light source is too large to characterize conventional nano-scale devices. Therefore, we have developed a measurement system for scanning photoemission microscopy (SPEM) using nano-beam focused by a Fresnel zone plate, and also have demonstrated nano-scale characterization of poly-Si gate pattern on high-k gate stack structures.